Presently, when lines of data are provided from a shared resource (e.g., memory) to caching agents (e.g., microprocessors) in response to a read access request, the initial coherency state (e.g., shared state, exclusive state, etc.) assigned to each line of data provided is always the same. For instance, some systems always provided a line in a shared state, while other systems always provided a line in an exclusive state. The initial coherency state to be assigned each line of data is typically integrated into the system design (e.g., hard-coded into memory controller logic). This is problematic because the same initial coherency state may not be suitable for every situation (e.g., every type of application, every line of data, and the like). As a result, system performance may be negatively affected.